Generally, photonic chips have interfaces to permit optical signals to be received from an optical source (e.g., a laser or an optical fiber) or transmitted to an optical fiber. One such method is edge coupling where the optical fiber is coupled with the edge of the photonic chip. As the level of integration, speed of operation, and functionality are increasing, photonic chips are running out of peripheral bond pad space to allow wire bond based interconnection to the underlying substrate or printed circuit board (PCB). Thus, photonic chips with Through Silicon Vias (TSVs) are highly desirable as they allow for higher density of interconnects and reduce the resistance as well as inductance associated with the wirebond connections. However, photonic chips with TSVs have several additional constraints on edge coupling. Wafers with TSVs are thinner (Typically in the range of 50 um to 150 um). Hence, even though shallow trenches in Si substrate are possible, deep trenches (typically created by Deep Reactive Ion Etching (DRIE)) cannot be created to for lens or fiber placement for an edge coupler. In addition, TSVs constrain the overall optical packaging or assembly since photonic chips with TSV must be attached to a glass or silicon interposer or a ceramic or an organic substrate using conventional solder reflow or thermal compression bonding processes. As such, conventional edge coupling techniques cannot be used with a photonic chip that has TSVs.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.